FPGA Implementation of Bose Chaudhuri Hocquenghem Code (BCH) Encoder and Decoder for Multiple Error Correction Control

Reduction of delay is a main concern in VLSI (Very Large Scale Integration), throughput of the CODEC is effectively increased. A (15, 7) BCH (Bose ChaudhuriHocquenghem Code) Encoder and Decoder for text message is implemented using Verilog HDL. BCH can corrected double error in any position of 15 bit codeword. Initially each character in a text message is converted into binary data of 7 bits. This 7 bit is encoded into 15 bit codeword. The corrected data is converted into an ASCII character. The decoder is implemented using the Peterson and chine’s Search algorithm. Simulation was carried out by using Xilinx simulator and verified results for an arbitrarily chosen message data.